diff --git a/Usb.cpp b/Usb.cpp
index 3ffbfbe4..d7fd44ce 100644
--- a/Usb.cpp
+++ b/Usb.cpp
@@ -579,24 +579,24 @@ uint8_t USB::AttemptConfig(uint8_t driver, uint8_t parent, uint8_t port, bool lo
                         // reset parent port
                         devConfig[parent]->ResetHubPort(port);
                 }
-        }
-        if (!rcode || rcode == USB_ERROR_CONFIG_REQUIRES_ADDITIONAL_RESET) {
+        } else if (rcode)
+                return rcode;
+
+        rcode = devConfig[driver]->Init(parent, port, lowspeed);
+        if (rcode == hrJERR) { // Some devices returns this when plugged in - trying to initialize the device again usually works
+                delay(100);
+                devConfig[driver]->ConfigureDevice(parent, port, lowspeed); // Just ignore the returned value
                 rcode = devConfig[driver]->Init(parent, port, lowspeed);
-                if (rcode == hrJERR) { // Some devices returns this when plugged in - trying to initialize the device again usually works
-                        delay(100);
-                        devConfig[driver]->ConfigureDevice(parent, port, lowspeed); // Just ignore the returned value
-                        rcode = devConfig[driver]->Init(parent, port, lowspeed);
-                }
-                if (rcode) {
-                        // Issue a bus reset, because the device may be in a limbo state
-                        if (parent == 0) {
-                                // Send a bus reset on the root interface.
-                                regWr(rHCTL, bmBUSRST); //issue bus reset
-                                delay(102); // delay 102ms, compensate for clock inaccuracy.
-                        } else {
-                                // reset parent port
-                                devConfig[parent]->ResetHubPort(port);
-                        }
+        }
+        if (rcode) {
+                // Issue a bus reset, because the device may be in a limbo state
+                if (parent == 0) {
+                        // Send a bus reset on the root interface.
+                        regWr(rHCTL, bmBUSRST); //issue bus reset
+                        delay(102); // delay 102ms, compensate for clock inaccuracy.
+                } else {
+                        // reset parent port
+                        devConfig[parent]->ResetHubPort(port);
                 }
         }
         return rcode;