17 #if !defined(__CDCPROLIFIC_H__)
18 #define __CDCPROLIFIC_H__
21 #include <avr/pgmspace.h>
28 #if defined(ARDUINO) && ARDUINO >=100
44 #define PL_PID ( 0x2303 || 0x0609 )
46 #define PROLIFIC_REV_H 0x0202
47 #define PROLIFIC_REV_X 0x0300
48 #define PROLIFIC_REV_HX_CHIP_D 0x0400
49 #define PROLIFIC_REV_1 0x0001
51 #define kXOnChar '\x11'
52 #define kXOffChar '\x13'
54 #define SPECIAL_SHIFT (5)
55 #define SPECIAL_MASK ((1<<SPECIAL_SHIFT) - 1)
56 #define STATE_ALL ( PD_RS232_S_MASK | PD_S_MASK )
57 #define FLOW_RX_AUTO ( PD_RS232_A_RFR | PD_RS232_A_DTR | PD_RS232_A_RXO )
58 #define FLOW_TX_AUTO ( PD_RS232_A_CTS | PD_RS232_A_DSR | PD_RS232_A_TXO | PD_RS232_A_DCD )
59 #define CAN_BE_AUTO ( FLOW_RX_AUTO | FLOW_TX_AUTO )
60 #define CAN_NOTIFY ( PD_RS232_N_MASK )
61 #define EXTERNAL_MASK ( PD_S_MASK | (PD_RS232_S_MASK & ~PD_RS232_S_LOOP) )
62 #define INTERNAL_DELAY ( PD_RS232_S_LOOP )
63 #define DEFAULT_AUTO ( PD_RS232_A_DTR | PD_RS232_A_RFR | PD_RS232_A_CTS | PD_RS232_A_DSR )
64 #define DEFAULT_NOTIFY 0x00
65 #define DEFAULT_STATE ( PD_S_TX_ENABLE | PD_S_RX_ENABLE | PD_RS232_A_TXO | PD_RS232_A_RXO )
67 #define CONTINUE_SEND 1
70 #define kRxAutoFlow ((UInt32)( PD_RS232_A_RFR | PD_RS232_A_DTR | PD_RS232_A_RXO ))
71 #define kTxAutoFlow ((UInt32)( PD_RS232_A_CTS | PD_RS232_A_DSR | PD_RS232_A_TXO | PD_RS232_A_DCD ))
72 #define kControl_StateMask ((UInt32)( PD_RS232_S_CTS | PD_RS232_S_DSR | PD_RS232_S_CAR | PD_RS232_S_RI ))
73 #define kRxQueueState ((UInt32)( PD_S_RXQ_EMPTY | PD_S_RXQ_LOW_WATER | PD_S_RXQ_HIGH_WATER | PD_S_RXQ_FULL ))
74 #define kTxQueueState ((UInt32)( PD_S_TXQ_EMPTY | PD_S_TXQ_LOW_WATER | PD_S_TXQ_HIGH_WATER | PD_S_TXQ_FULL ))
76 #define kCONTROL_DTR 0x01
77 #define kCONTROL_RTS 0x02
89 #define kStateTransientMask 0x74
90 #define kBreakError 0x04
91 #define kFrameError 0x10
92 #define kParityError 0x20
93 #define kOverrunError 0x40
99 #define kHandshakeInMask ((UInt32)( PD_RS232_S_CTS | PD_RS232_S_DSR | PD_RS232_S_CAR | PD_RS232_S_RI ))
101 #define VENDOR_WRITE_REQUEST_TYPE 0x40
102 #define VENDOR_WRITE_REQUEST 0x01
104 #define VENDOR_READ_REQUEST_TYPE 0xc0
105 #define VENDOR_READ_REQUEST 0x01
108 #define SET_DCR0 0x00
109 #define GET_DCR0 0x80
110 #define DCR0_INIT 0x01
111 #define DCR0_INIT_H 0x41
112 #define DCR0_INIT_X 0x61
114 #define SET_DCR1 0x01
115 #define GET_DCR1 0x81
116 #define DCR1_INIT_H 0x80
117 #define DCR1_INIT_X 0x00
119 #define SET_DCR2 0x02
120 #define GET_DCR2 0x82
121 #define DCR2_INIT_H 0x24
122 #define DCR2_INIT_X 0x44
125 #define RESET_DOWNSTREAM_DATA_PIPE 0x08
126 #define RESET_UPSTREAM_DATA_PIPE 0x09
139 #define PL_MAX_ENDPOINTS 4
153 virtual uint8_t
Init(uint8_t parent, uint8_t port,
bool lowspeed);
163 uint8_t vendorRead( uint8_t val_lo, uint8_t val_hi, uint16_t index, uint8_t* buf );
164 uint8_t vendorWrite( uint8_t val_lo, uint8_t val_hi, uint8_t index );
168 inline uint8_t PL2303::vendorRead( uint8_t val_lo, uint8_t val_hi, uint16_t index, uint8_t* buf )
170 return(
pUsb->
ctrlReq(
bAddress, 0,
VENDOR_READ_REQUEST_TYPE,
VENDOR_READ_REQUEST, val_lo, val_hi, index, 1, 1, buf, NULL ));
174 inline uint8_t PL2303::vendorWrite( uint8_t val_lo, uint8_t val_hi, uint8_t index )
176 return(
pUsb->
ctrlReq(
bAddress, 0,
VENDOR_WRITE_REQUEST_TYPE,
VENDOR_WRITE_REQUEST, val_lo, val_hi, index, 0, 0, NULL, NULL ));
179 #endif // __CDCPROLIFIC_H__