mirror of
https://github.com/felis/USB_Host_Shield_2.0.git
synced 2024-03-22 11:31:26 +01:00
294 lines
9.4 KiB
C++
294 lines
9.4 KiB
C++
/* MAX3421E-based USB Host Library header file */
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#ifndef _USBHOST_H_
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#define _USBHOST_H_
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#include <WProgram.h>
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#include "avrpins.h"
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#include "max3421e.h"
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#include "usb_ch9.h"
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/* SPI initialization */
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template< typename CLK, typename MOSI, typename MISO, typename SPI_SS > class SPi
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{
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public:
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static void init() {
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uint8_t tmp;
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CLK::SetDirWrite();
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MOSI::SetDirWrite();
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MISO::SetDirRead();
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SPI_SS::SetDirWrite();
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/* mode 00 (CPOL=0, CPHA=0) master, fclk/2. Mode 11 (CPOL=11, CPHA=11) is also supported by MAX3421E */
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SPCR = 0x50;
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SPSR = 0x01;
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/**/
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tmp = SPSR;
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tmp = SPDR;
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}
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};
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/* SPI pin definitions. see avrpins.h */
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#if defined(__AVR_ATmega1280__) || (__AVR_ATmega2560__)
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typedef SPi< Pb1, Pb2, Pb3, Pb0 > spi;
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#endif
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#if defined(__AVR_ATmega168__) || defined(__AVR_ATmega328P__)
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typedef SPi< Pb5, Pb3, Pb4, Pb2 > spi;
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#endif
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template< typename SS, typename INTR > class MAX3421e /* : public spi */
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{
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static uint8_t vbusState;
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public:
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MAX3421e();
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void regWr( uint8_t reg, uint8_t data );
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uint8_t* bytesWr( uint8_t reg, uint8_t nbytes, uint8_t* data_p );
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void gpioWr( uint8_t data );
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uint8_t regRd( uint8_t reg );
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uint8_t* bytesRd( uint8_t reg, uint8_t nbytes, uint8_t* data_p );
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uint8_t gpioRd();
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uint16_t reset();
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int8_t Init();
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uint8_t getVbusState( void ) { return vbusState; };
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void busprobe();
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uint8_t GpxHandler();
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uint8_t IntHandler();
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uint8_t Task();
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};
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template< typename SS, typename INTR >
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uint8_t MAX3421e< SS, INTR >::vbusState = 0;
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/* constructor */
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template< typename SS, typename INTR >
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MAX3421e< SS, INTR >::MAX3421e()
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{
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/* pin and peripheral setup */
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SS::SetDirWrite();
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SS::Set();
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/* For shield rev.1.xx uncomment following two lines */
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P7::SetDirWrite();
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P7::Set();
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spi::init();
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INTR::SetDirRead();
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/* MAX3421E - full-duplex SPI, level interrupt */
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regWr( rPINCTL,( bmFDUPSPI + bmINTLEVEL ));
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};
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/* write single byte into MAX3421 register */
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template< typename SS, typename INTR >
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void MAX3421e< SS, INTR >::regWr( uint8_t reg, uint8_t data )
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{
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SS::Clear();
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SPDR = ( reg | 0x02 );
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while(!( SPSR & ( 1 << SPIF )));
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SPDR = data;
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while(!( SPSR & ( 1 << SPIF )));
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SS::Set();
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return;
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};
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/* multiple-byte write */
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/* returns a pointer to memory position after last written */
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template< typename SS, typename INTR >
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uint8_t* MAX3421e< SS, INTR >::bytesWr( uint8_t reg, uint8_t nbytes, uint8_t* data_p )
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{
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SS::Clear();
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SPDR = ( reg | 0x02 ); //set WR bit and send register number
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while( nbytes-- ) {
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while(!( SPSR & ( 1 << SPIF ))); //check if previous byte was sent
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SPDR = ( *data_p ); // send next data byte
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data_p++; // advance data pointer
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}
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while(!( SPSR & ( 1 << SPIF )));
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SS::Set();
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return( data_p );
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}
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/* GPIO write */
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/*GPIO byte is split between 2 registers, so two writes are needed to write one byte */
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/* GPOUT bits are in the low nibble. 0-3 in IOPINS1, 4-7 in IOPINS2 */
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template< typename SS, typename INTR >
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void MAX3421e< SS, INTR >::gpioWr( uint8_t data )
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{
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regWr( rIOPINS1, data );
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data >>= 4;
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regWr( rIOPINS2, data );
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return;
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}
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/* single host register read */
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template< typename SS, typename INTR >
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uint8_t MAX3421e< SS, INTR >::regRd( uint8_t reg )
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{
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SS::Clear();
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SPDR = reg;
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while(!( SPSR & ( 1 << SPIF )));
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SPDR = 0; //send empty byte
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while(!( SPSR & ( 1 << SPIF )));
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SS::Set();
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return( SPDR );
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}
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/* multiple-byte register read */
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/* returns a pointer to a memory position after last read */
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template< typename SS, typename INTR >
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uint8_t* MAX3421e< SS, INTR >::bytesRd( uint8_t reg, uint8_t nbytes, uint8_t* data_p )
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{
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SS::Clear();
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SPDR = reg;
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while(!( SPSR & ( 1 << SPIF ))); //wait
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while( nbytes ) {
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SPDR = 0; //send empty byte
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nbytes--;
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while(!( SPSR & ( 1 << SPIF )));
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*data_p = SPDR;
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data_p++;
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}
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SS::Set();
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return( data_p );
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}
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/* GPIO read. See gpioWr for explanation */
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/* GPIN pins are in high nibbles of IOPINS1, IOPINS2 */
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template< typename SS, typename INTR >
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uint8_t MAX3421e< SS, INTR >::gpioRd()
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{
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uint8_t gpin = 0;
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gpin = regRd( rIOPINS2 ); //pins 4-7
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gpin &= 0xf0; //clean lower nibble
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gpin |= ( regRd( rIOPINS1 ) >>4 ) ; //shift low bits and OR with upper from previous operation.
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return( gpin );
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}
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/* reset MAX3421E. Returns number of cycles it took for PLL to stabilize after reset
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or zero if PLL haven't stabilized in 65535 cycles */
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template< typename SS, typename INTR >
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uint16_t MAX3421e< SS, INTR >::reset()
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{
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uint16_t i = 0;
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regWr( rUSBCTL, bmCHIPRES );
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regWr( rUSBCTL, 0x00 );
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while( ++i ) {
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if(( regRd( rUSBIRQ ) & bmOSCOKIRQ )) {
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break;
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}
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}
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return( i );
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}
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///* initialize MAX3421E. Set Host mode, pullups, and stuff. Returns 0 if success, -1 if not */
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//template< typename SS, typename INTR >
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//int8_t MAX3421e< SS, INTR >::Init()
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//{
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// if( reset() == 0 ) { //OSCOKIRQ hasn't asserted in time
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// return ( -1 );
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// }
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// regWr( rMODE, bmDPPULLDN|bmDMPULLDN|bmHOST ); // set pull-downs, Host
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//
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// return( 0 );
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//}
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/* initialize MAX3421E. Set Host mode, pullups, and stuff. Returns 0 if success, -1 if not */
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template< typename SS, typename INTR >
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int8_t MAX3421e< SS, INTR >::Init()
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{
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if( reset() == 0 )
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{ //OSCOKIRQ hasn't asserted in time
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return ( -1 );
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}
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regWr( rMODE, bmDPPULLDN|bmDMPULLDN|bmHOST ); // set pull-downs, Host
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regWr( rHIEN, bmCONDETIE|bmFRAMEIE ); //connection detection
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/* check if device is connected */
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regWr( rHCTL,bmSAMPLEBUS ); // sample USB bus
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while(!(regRd( rHCTL ) & bmSAMPLEBUS )); //wait for sample operation to finish
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busprobe(); //check if anything is connected
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regWr( rHIRQ, bmCONDETIRQ ); //clear connection detect interrupt
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regWr( rCPUCTL, 0x01 ); //enable interrupt pin
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return( 0 );
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}
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/* probe bus to determine device presense and speed and switch host to this speed */
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template< typename SS, typename INTR >
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void MAX3421e< SS, INTR >::busprobe()
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{
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uint8_t bus_sample;
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bus_sample = regRd( rHRSL ); //Get J,K status
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bus_sample &= ( bmJSTATUS|bmKSTATUS ); //zero the rest of the byte
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switch( bus_sample ) { //start full-speed or low-speed host
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case( bmJSTATUS ):
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if(( regRd( rMODE ) & bmLOWSPEED ) == 0 ) {
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regWr( rMODE, MODE_FS_HOST ); //start full-speed host
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vbusState = FSHOST;
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}
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else {
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regWr( rMODE, MODE_LS_HOST); //start low-speed host
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vbusState = LSHOST;
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}
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break;
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case( bmKSTATUS ):
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if(( regRd( rMODE ) & bmLOWSPEED ) == 0 ) {
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regWr( rMODE, MODE_LS_HOST ); //start low-speed host
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vbusState = LSHOST;
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}
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else {
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regWr( rMODE, MODE_FS_HOST ); //start full-speed host
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vbusState = FSHOST;
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}
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break;
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case( bmSE1 ): //illegal state
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vbusState = SE1;
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break;
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case( bmSE0 ): //disconnected state
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vbusState = SE0;
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break;
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}//end switch( bus_sample )
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}
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/* MAX3421 state change task and interrupt handler */
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template< typename SS, typename INTR >
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uint8_t MAX3421e< SS, INTR >::Task( void )
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{
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uint8_t rcode = 0;
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uint8_t pinvalue;
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//Serial.print("Vbus state: ");
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//Serial.println( vbusState, HEX );
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pinvalue = INTR::IsSet(); //Read();
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//pinvalue = digitalRead( MAX_INT );
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if( pinvalue == LOW ) {
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rcode = IntHandler();
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}
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// pinvalue = digitalRead( MAX_GPX );
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// if( pinvalue == LOW ) {
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// GpxHandler();
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// }
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// usbSM(); //USB state machine
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return( rcode );
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}
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template< typename SS, typename INTR >
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uint8_t MAX3421e< SS, INTR >::IntHandler()
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{
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uint8_t HIRQ;
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uint8_t HIRQ_sendback = 0x00;
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HIRQ = regRd( rHIRQ ); //determine interrupt source
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//if( HIRQ & bmFRAMEIRQ ) { //->1ms SOF interrupt handler
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// HIRQ_sendback |= bmFRAMEIRQ;
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//}//end FRAMEIRQ handling
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if( HIRQ & bmCONDETIRQ ) {
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busprobe();
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HIRQ_sendback |= bmCONDETIRQ;
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}
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/* End HIRQ interrupts handling, clear serviced IRQs */
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regWr( rHIRQ, HIRQ_sendback );
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return( HIRQ_sendback );
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}
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//template< typename SS, typename INTR >
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//uint8_t MAX3421e< SS, INTR >::GpxHandler()
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//{
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// uint8_t GPINIRQ = regRd( rGPINIRQ ); //read GPIN IRQ register
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//// if( GPINIRQ & bmGPINIRQ7 ) { //vbus overload
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//// vbusPwr( OFF ); //attempt powercycle
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//// delay( 1000 );
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//// vbusPwr( ON );
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//// regWr( rGPINIRQ, bmGPINIRQ7 );
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//// }
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// return( GPINIRQ );
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//}
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#endif //_USBHOST_H_
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