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Classes</h2></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">class  </td><td class="memItemRight" valign="bottom"><a class="el" href="class_x_r21_b1411.html">XR21B1411</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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Macros</h2></td></tr>
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<tr class="memitem:a8e9903788e0c8f15dbb205b8c6a8d915"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a8e9903788e0c8f15dbb205b8c6a8d915">XR_REG_CUSTOM_DRIVER</a>   (0x020DU)</td></tr>
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<tr class="separator:a8e9903788e0c8f15dbb205b8c6a8d915"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a075ef14c8f095226cca6ede02ad47330"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a075ef14c8f095226cca6ede02ad47330">XR_REG_CUSTOM_DRIVER_ACTIVE</a>   (0x0001U)</td></tr>
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<tr class="separator:a075ef14c8f095226cca6ede02ad47330"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a25ef72a2a8aa0a220829d329fb785645"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a25ef72a2a8aa0a220829d329fb785645">XR_REG_ACM_FLOW_CTL</a>   (0x0216U)</td></tr>
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<tr class="separator:a25ef72a2a8aa0a220829d329fb785645"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abc0a46d85c6df0beccc11db5d7d2d5a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#abc0a46d85c6df0beccc11db5d7d2d5a3">XR_REG_FLOW_CTL</a>   (0x0C06U)</td></tr>
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<tr class="separator:abc0a46d85c6df0beccc11db5d7d2d5a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a30213ba09248c33b8de14cdf016f7a2b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a30213ba09248c33b8de14cdf016f7a2b">XR_REG_FLOW_CTL_HALF_DPLX</a>   (0x0008U)</td></tr>
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<tr class="separator:a30213ba09248c33b8de14cdf016f7a2b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac8a391ed7f9637b7ae890493e3a3a6db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#ac8a391ed7f9637b7ae890493e3a3a6db">XR_REG_FLOW_CTL_MODE_MASK</a>   (0x0007U)</td></tr>
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<tr class="separator:ac8a391ed7f9637b7ae890493e3a3a6db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a83a79192b21718ad83a24e40bc5bb2aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a83a79192b21718ad83a24e40bc5bb2aa">XR_REG_FLOW_CTL_NONE</a>   (0x0000U)</td></tr>
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<tr class="separator:a83a79192b21718ad83a24e40bc5bb2aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1002d05086f8a743ee27d1f34ef59236"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a1002d05086f8a743ee27d1f34ef59236">XR_REG_FLOW_CTL_HW</a>   (0x0001U)</td></tr>
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<tr class="separator:a1002d05086f8a743ee27d1f34ef59236"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a726a4183ba22b46b1fc4ad202b1ac67e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a726a4183ba22b46b1fc4ad202b1ac67e">XR_REG_FLOW_CTL_SW</a>   (0x0002U)</td></tr>
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<tr class="separator:a726a4183ba22b46b1fc4ad202b1ac67e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a26a1ddfd2e6eab67d736f1ad3243aa17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a26a1ddfd2e6eab67d736f1ad3243aa17">XR_REG_FLOW_CTL_MMMRX</a>   (0x0003U)</td></tr>
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<tr class="separator:a26a1ddfd2e6eab67d736f1ad3243aa17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a72a8f76bc99063221e9f43e958ba809d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a72a8f76bc99063221e9f43e958ba809d">XR_REG_FLOW_CTL_MMMRXTX</a>   (0x0004U)</td></tr>
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<tr class="separator:a72a8f76bc99063221e9f43e958ba809d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afcbf11fa6130c11af3fc99db0e594ebe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#afcbf11fa6130c11af3fc99db0e594ebe">XR_REG_ACM_GPIO_MODE</a>   (0x0217U)</td></tr>
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<tr class="separator:afcbf11fa6130c11af3fc99db0e594ebe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae0cc1ba6c0ca0d87f3e6a285c516dac1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#ae0cc1ba6c0ca0d87f3e6a285c516dac1">XR_REG_GPIO_MODE</a>   (0x0C0CU)</td></tr>
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<tr class="separator:ae0cc1ba6c0ca0d87f3e6a285c516dac1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a51fdd6197f62ac4f0a934d7936c8ee34"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a51fdd6197f62ac4f0a934d7936c8ee34">XR_REG_GPIO_MODE_GPIO</a>   (0x0000U)</td></tr>
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<tr class="separator:a51fdd6197f62ac4f0a934d7936c8ee34"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a61ab7cdf866011bf637ebd44773419c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a61ab7cdf866011bf637ebd44773419c6">XR_REG_GPIO_MODE_FC_RTSCTS</a>   (0x0001U)</td></tr>
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<tr class="separator:a61ab7cdf866011bf637ebd44773419c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a48c14c5fad907a174d66fd1b0a2f79aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a48c14c5fad907a174d66fd1b0a2f79aa">XR_REG_GPIO_MODE_FC_DTRDSR</a>   (0x0002U)</td></tr>
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<tr class="separator:a48c14c5fad907a174d66fd1b0a2f79aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab20e3738acf655de3739e72aeab96c09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#ab20e3738acf655de3739e72aeab96c09">XR_REG_GPIO_MODE_ATE</a>   (0x0003U)</td></tr>
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<tr class="separator:ab20e3738acf655de3739e72aeab96c09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a081f72423d31521636a722f7a492b1cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a081f72423d31521636a722f7a492b1cc">XR_REG_GPIO_MODE_ATE_ADDRESS</a>   (0x0004U)</td></tr>
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<tr class="separator:a081f72423d31521636a722f7a492b1cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1cb510c50f3eec4bee2e42e639583e56"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a1cb510c50f3eec4bee2e42e639583e56">XR_REG_ACM_GPIO_DIR</a>   (0x0218U)</td></tr>
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<tr class="separator:a1cb510c50f3eec4bee2e42e639583e56"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a63a2f278653364208a91fcc92508088a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a63a2f278653364208a91fcc92508088a">XR_REG_GPIO_DIR</a>   (0x0C0DU)</td></tr>
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<tr class="separator:a63a2f278653364208a91fcc92508088a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad5713c55a6526b33700798c405c318cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#ad5713c55a6526b33700798c405c318cc">XR_REG_ACM_GPIO_INT</a>   (0x0219U)</td></tr>
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<tr class="separator:ad5713c55a6526b33700798c405c318cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae7bfc6468784d894cdc775d95b55cda5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#ae7bfc6468784d894cdc775d95b55cda5">XR_REG_GPIO_INT</a>   (0x0C11U)</td></tr>
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<tr class="separator:ae7bfc6468784d894cdc775d95b55cda5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab1ceb2e703f17467c42e9cf6b1e3ff07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#ab1ceb2e703f17467c42e9cf6b1e3ff07">XR_REG_GPIO_MASK</a>   (0x001FU)</td></tr>
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<tr class="separator:ab1ceb2e703f17467c42e9cf6b1e3ff07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7e4e23aeae9aadb1eed89627386655c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a7e4e23aeae9aadb1eed89627386655c6">XR_REG_UART_ENABLE</a>   (0x0C00U)</td></tr>
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<tr class="separator:a7e4e23aeae9aadb1eed89627386655c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9bbf0d7a31d01440f001ab729d9953ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a9bbf0d7a31d01440f001ab729d9953ec">XR_REG_UART_ENABLE_RX</a>   (0x0002U)</td></tr>
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<tr class="separator:a9bbf0d7a31d01440f001ab729d9953ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a68d9b17ee2af74624e2fff60815bee3e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a68d9b17ee2af74624e2fff60815bee3e">XR_REG_UART_ENABLE_TX</a>   (0x0001U)</td></tr>
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<tr class="memitem:af50fcb0d47dfcb8dae3020b98b90f5b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#af50fcb0d47dfcb8dae3020b98b90f5b1">XR_REG_ERROR_STATUS</a>   (0x0C09U)</td></tr>
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<tr class="memitem:ae8dbffb7f958e6a5c0c0727dcebe8851"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#ae8dbffb7f958e6a5c0c0727dcebe8851">XR_REG_ERROR_STATUS_MASK</a>   (0x00F8U)</td></tr>
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<tr class="memitem:aa62ce08310e0d1e091d826bae6a091a0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#aa62ce08310e0d1e091d826bae6a091a0">XR_REG_ERROR_STATUS_ERROR</a>   (0x0070U)</td></tr>
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<tr class="memitem:af2eb9c3a6ad7f95fc439139f8c430d74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#af2eb9c3a6ad7f95fc439139f8c430d74">XR_REG_ERROR_STATUS_BREAK</a>   (0x0008U)</td></tr>
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<tr class="memitem:ada3426d2e814492af6445b884b2eeae4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#ada3426d2e814492af6445b884b2eeae4">XR_REG_ERROR_STATUS_OVERRUN</a>   (0x0010U)</td></tr>
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<tr class="memitem:a569c29af1276f5cd38be163292549c05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a569c29af1276f5cd38be163292549c05">XR_REG_ERROR_STATUS_PARITY</a>   (0x0020U)</td></tr>
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<tr class="memitem:a6d68869ec17604caec0a490cd4e84191"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a6d68869ec17604caec0a490cd4e84191">XR_REG_ERROR_STATUS_FRAME</a>   (0x0040U)</td></tr>
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<tr class="memitem:af7c8d263bd77298510c4e361b52f6fb6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#af7c8d263bd77298510c4e361b52f6fb6">XR_REG_ERROR_STATUS_BREAKING</a>   (0x0080U)</td></tr>
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<tr class="memitem:aee14dd1ab1c86dcad774faab303137cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#aee14dd1ab1c86dcad774faab303137cd">XR_REG_TX_BREAK</a>   (0x0C0AU)</td></tr>
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<tr class="memitem:af22908da2ee1a71f46676c63f311e3e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#af22908da2ee1a71f46676c63f311e3e9">XR_REG_XCVR_EN_DELAY</a>   (0x0C0BU)</td></tr>
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<tr class="separator:af22908da2ee1a71f46676c63f311e3e9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a20516180546c38027db39386f2d6106e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a20516180546c38027db39386f2d6106e">XR_REG_GPIO_SET</a>   (0x0C0EU)</td></tr>
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<tr class="memitem:a8af2993c69324d86f6b99ddbb46d1a79"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a8af2993c69324d86f6b99ddbb46d1a79">XR_REG_GPIO_CLR</a>   (0x0C0FU)</td></tr>
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<tr class="memitem:a185a5adb2f83548877a5d223c8552cb2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a185a5adb2f83548877a5d223c8552cb2">XR_REG_GPIO_STATUS</a>   (0x0C10U)</td></tr>
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<tr class="memitem:ad8f26622feeb072c9caa5c5f95f3b6ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#ad8f26622feeb072c9caa5c5f95f3b6ed">XR_REG_CUSTOMISED_INT</a>   (0x0C12U)</td></tr>
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<tr class="memitem:aceefd29123950f37931cadd773071efa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#aceefd29123950f37931cadd773071efa">XR_REG_PIN_PULLUP_ENABLE</a>   (0x0C14U)</td></tr>
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<tr class="memitem:a83d70ff79812574989ab2ceda9636270"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a83d70ff79812574989ab2ceda9636270">XR_REG_PIN_PULLDOWN_ENABLE</a>   (0x0C15U)</td></tr>
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<tr class="memitem:aea7f6edeac7de9f93cd6227d04e278e1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#aea7f6edeac7de9f93cd6227d04e278e1">XR_REG_LOOPBACK</a>   (0x0C16U)</td></tr>
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<tr class="memitem:afbb1095c827131f5b8d678b17112f957"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#afbb1095c827131f5b8d678b17112f957">XR_REG_RX_FIFO_LATENCY</a>   (0x0CC2U)</td></tr>
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<tr class="memitem:a655ecdd5b1700c278a086801e8e61a58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a655ecdd5b1700c278a086801e8e61a58">XR_REG_RX_FIFO_LATENCY_ENABLE</a>   (0x0001U)</td></tr>
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<tr class="separator:a655ecdd5b1700c278a086801e8e61a58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a937d425ec40f212dd74734aec73231e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a937d425ec40f212dd74734aec73231e3">XR_REG_WIDE_MODE</a>   (0x0D02U)</td></tr>
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<tr class="memitem:ac1d8e20f5e98118493fb0947c2b43962"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#ac1d8e20f5e98118493fb0947c2b43962">XR_REG_WIDE_MODE_ENABLE</a>   (0x0001U)</td></tr>
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<tr class="memitem:a2a1d62d79a513b81dde469959e52d177"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a2a1d62d79a513b81dde469959e52d177">XR_REG_XON_CHAR</a>   (0x0C07U)</td></tr>
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<tr class="memitem:a0406654de77bbf9fc1202614e30e66bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a0406654de77bbf9fc1202614e30e66bb">XR_REG_XOFF_CHAR</a>   (0x0C08U)</td></tr>
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<tr class="memitem:a114fb71c507d633a1b95316353e086cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a114fb71c507d633a1b95316353e086cd">XR_REG_TX_FIFO_RESET</a>   (0x0C80U)</td></tr>
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<tr class="memitem:a73b11cca22f961553a50adb669cff1f0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a73b11cca22f961553a50adb669cff1f0">XR_REG_TX_FIFO_COUNT</a>   (0x0C81U)</td></tr>
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<tr class="memitem:a3c166581fd6ce5bc95a7f80b8cdfadee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a3c166581fd6ce5bc95a7f80b8cdfadee">XR_REG_RX_FIFO_RESET</a>   (0x0CC0U)</td></tr>
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<tr class="memitem:a901ae4a2b7b7faab5b8bee17d2d18fd0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a901ae4a2b7b7faab5b8bee17d2d18fd0">XR_REG_RX_FIFO_COUNT</a>   (0x0CC1U)</td></tr>
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<tr class="memitem:a8c8ce6038c7bf52b5cca11cb42181624"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a8c8ce6038c7bf52b5cca11cb42181624">XR_WRITE_REQUEST_TYPE</a>   (0x40U)</td></tr>
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<tr class="memitem:a593d617a7a12d2b729f10199a4d0b152"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a593d617a7a12d2b729f10199a4d0b152">XR_READ_REQUEST_TYPE</a>   (0xC0U)</td></tr>
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<tr class="memitem:a11b56c2a67be0b666f282b3b78c1aa38"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="cdc___x_r21_b1411_8h.html#a11b56c2a67be0b666f282b3b78c1aa38">XR_MAX_ENDPOINTS</a>   4</td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
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<td class="memname">#define XR_REG_CUSTOM_DRIVER   (0x020DU)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00024">24</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_CUSTOM_DRIVER_ACTIVE   (0x0001U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00025">25</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_ACM_FLOW_CTL   (0x0216U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00027">27</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_FLOW_CTL   (0x0C06U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00028">28</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_FLOW_CTL_HALF_DPLX   (0x0008U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00029">29</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_FLOW_CTL_MODE_MASK   (0x0007U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00030">30</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_FLOW_CTL_NONE   (0x0000U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00031">31</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_FLOW_CTL_HW   (0x0001U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00032">32</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_FLOW_CTL_SW   (0x0002U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00033">33</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_FLOW_CTL_MMMRX   (0x0003U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00034">34</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_FLOW_CTL_MMMRXTX   (0x0004U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00035">35</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_ACM_GPIO_MODE   (0x0217U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00037">37</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_GPIO_MODE   (0x0C0CU)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00038">38</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_GPIO_MODE_GPIO   (0x0000U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00039">39</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_GPIO_MODE_FC_RTSCTS   (0x0001U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00040">40</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_GPIO_MODE_FC_DTRDSR   (0x0002U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00041">41</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_GPIO_MODE_ATE   (0x0003U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00042">42</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_GPIO_MODE_ATE_ADDRESS   (0x0004U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00043">43</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_ACM_GPIO_DIR   (0x0218U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00045">45</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_GPIO_DIR   (0x0C0DU)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00046">46</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_ACM_GPIO_INT   (0x0219U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00048">48</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<a class="anchor" id="ae7bfc6468784d894cdc775d95b55cda5"></a>
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<td class="memname">#define XR_REG_GPIO_INT   (0x0C11U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00049">49</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_GPIO_MASK   (0x001FU)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00050">50</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_UART_ENABLE   (0x0C00U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00052">52</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<a class="anchor" id="a9bbf0d7a31d01440f001ab729d9953ec"></a>
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<td class="memname">#define XR_REG_UART_ENABLE_RX   (0x0002U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00053">53</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_UART_ENABLE_TX   (0x0001U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00054">54</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_ERROR_STATUS   (0x0C09U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00056">56</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_ERROR_STATUS_MASK   (0x00F8U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00057">57</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_ERROR_STATUS_ERROR   (0x0070U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00058">58</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_ERROR_STATUS_BREAK   (0x0008U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00059">59</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_ERROR_STATUS_OVERRUN   (0x0010U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00060">60</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_ERROR_STATUS_PARITY   (0x0020U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00061">61</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_ERROR_STATUS_FRAME   (0x0040U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00062">62</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_ERROR_STATUS_BREAKING   (0x0080U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00063">63</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_TX_BREAK   (0x0C0AU)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00065">65</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_XCVR_EN_DELAY   (0x0C0BU)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00067">67</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_GPIO_SET   (0x0C0EU)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00069">69</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_GPIO_CLR   (0x0C0FU)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00071">71</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_GPIO_STATUS   (0x0C10U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00073">73</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<a class="anchor" id="ad8f26622feeb072c9caa5c5f95f3b6ed"></a>
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<td class="memname">#define XR_REG_CUSTOMISED_INT   (0x0C12U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00075">75</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<a class="anchor" id="aceefd29123950f37931cadd773071efa"></a>
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<td class="memname">#define XR_REG_PIN_PULLUP_ENABLE   (0x0C14U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00077">77</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_PIN_PULLDOWN_ENABLE   (0x0C15U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00079">79</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<a class="anchor" id="aea7f6edeac7de9f93cd6227d04e278e1"></a>
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<td class="memname">#define XR_REG_LOOPBACK   (0x0C16U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00081">81</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<a class="anchor" id="afbb1095c827131f5b8d678b17112f957"></a>
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<td class="memname">#define XR_REG_RX_FIFO_LATENCY   (0x0CC2U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00083">83</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<a class="anchor" id="a655ecdd5b1700c278a086801e8e61a58"></a>
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<td class="memname">#define XR_REG_RX_FIFO_LATENCY_ENABLE   (0x0001U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00084">84</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<a class="anchor" id="a937d425ec40f212dd74734aec73231e3"></a>
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<td class="memname">#define XR_REG_WIDE_MODE   (0x0D02U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00086">86</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<a class="anchor" id="ac1d8e20f5e98118493fb0947c2b43962"></a>
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<td class="memname">#define XR_REG_WIDE_MODE_ENABLE   (0x0001U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00087">87</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<a class="anchor" id="a2a1d62d79a513b81dde469959e52d177"></a>
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<td class="memname">#define XR_REG_XON_CHAR   (0x0C07U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00089">89</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<a class="anchor" id="a0406654de77bbf9fc1202614e30e66bb"></a>
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<td class="memname">#define XR_REG_XOFF_CHAR   (0x0C08U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00090">90</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<a class="anchor" id="a114fb71c507d633a1b95316353e086cd"></a>
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<td class="memname">#define XR_REG_TX_FIFO_RESET   (0x0C80U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00092">92</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<a class="anchor" id="a73b11cca22f961553a50adb669cff1f0"></a>
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<td class="memname">#define XR_REG_TX_FIFO_COUNT   (0x0C81U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00093">93</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<a class="anchor" id="a3c166581fd6ce5bc95a7f80b8cdfadee"></a>
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<td class="memname">#define XR_REG_RX_FIFO_RESET   (0x0CC0U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00094">94</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<td class="memname">#define XR_REG_RX_FIFO_COUNT   (0x0CC1U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00095">95</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<a class="anchor" id="a8c8ce6038c7bf52b5cca11cb42181624"></a>
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<td class="memname">#define XR_WRITE_REQUEST_TYPE   (0x40U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00097">97</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<a class="anchor" id="a593d617a7a12d2b729f10199a4d0b152"></a>
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<td class="memname">#define XR_READ_REQUEST_TYPE   (0xC0U)</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00099">99</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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<a class="anchor" id="a11b56c2a67be0b666f282b3b78c1aa38"></a>
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<td class="memname">#define XR_MAX_ENDPOINTS   4</td>
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<p>Definition at line <a class="el" href="cdc___x_r21_b1411_8h_source.html#l00101">101</a> of file <a class="el" href="cdc___x_r21_b1411_8h_source.html">cdc_XR21B1411.h</a>.</p>
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