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Renamed CLK, MOSI, MISO and SS variables, as they conflicted with defines in pins_arduino.h

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See: 7fcba37acf
This commit is contained in:
Kristian Lauszus 2013-12-15 22:19:50 +01:00
parent 0b2e444e7b
commit f283e90402
1 changed files with 48 additions and 48 deletions
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96
usbhost.h
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@ -28,7 +28,7 @@ e-mail : support@circuitsathome.com
#endif #endif
/* SPI initialization */ /* SPI initialization */
template< typename CLK, typename MOSI, typename MISO, typename SPI_SS > class SPi { template< typename SPI_CLK, typename SPI_MOSI, typename SPI_MISO, typename SPI_SS > class SPi {
#if USING_SPI4TEENSY3 #if USING_SPI4TEENSY3
public: public:
@ -46,9 +46,9 @@ public:
static void init() { static void init() {
//uint8_t tmp; //uint8_t tmp;
CLK::SetDirWrite(); SPI_CLK::SetDirWrite();
MOSI::SetDirWrite(); SPI_MOSI::SetDirWrite();
MISO::SetDirRead(); SPI_MISO::SetDirRead();
SPI_SS::SetDirWrite(); SPI_SS::SetDirWrite();
/* mode 00 (CPOL=0, CPHA=0) master, fclk/2. Mode 11 (CPOL=11, CPHA=11) is also supported by MAX3421E */ /* mode 00 (CPOL=0, CPHA=0) master, fclk/2. Mode 11 (CPOL=11, CPHA=11) is also supported by MAX3421E */
SPCR = 0x50; SPCR = 0x50;
@ -78,7 +78,7 @@ typedef enum {
vbus_off = GPX_VBDET vbus_off = GPX_VBDET
} VBUS_t; } VBUS_t;
template< typename SS, typename INTR > class MAX3421e /* : public spi */ { template< typename SPI_SS, typename INTR > class MAX3421e /* : public spi */ {
static uint8_t vbusState; static uint8_t vbusState;
public: public:
@ -106,12 +106,12 @@ public:
uint8_t Task(); uint8_t Task();
}; };
template< typename SS, typename INTR > template< typename SPI_SS, typename INTR >
uint8_t MAX3421e< SS, INTR >::vbusState = 0; uint8_t MAX3421e< SPI_SS, INTR >::vbusState = 0;
/* constructor */ /* constructor */
template< typename SS, typename INTR > template< typename SPI_SS, typename INTR >
MAX3421e< SS, INTR >::MAX3421e() { MAX3421e< SPI_SS, INTR >::MAX3421e() {
// Leaving ADK hardware setup in here, for now. This really belongs with the other parts. // Leaving ADK hardware setup in here, for now. This really belongs with the other parts.
#ifdef BOARD_MEGA_ADK #ifdef BOARD_MEGA_ADK
// For Mega ADK, which has a Max3421e on-board, set MAX_RESET to output mode, and then set it to HIGH // For Mega ADK, which has a Max3421e on-board, set MAX_RESET to output mode, and then set it to HIGH
@ -121,10 +121,10 @@ MAX3421e< SS, INTR >::MAX3421e() {
}; };
/* write single byte into MAX3421 register */ /* write single byte into MAX3421 register */
template< typename SS, typename INTR > template< typename SPI_SS, typename INTR >
void MAX3421e< SS, INTR >::regWr(uint8_t reg, uint8_t data) { void MAX3421e< SPI_SS, INTR >::regWr(uint8_t reg, uint8_t data) {
XMEM_ACQUIRE_SPI(); XMEM_ACQUIRE_SPI();
SS::Clear(); SPI_SS::Clear();
#if USING_SPI4TEENSY3 #if USING_SPI4TEENSY3
uint8_t c[2]; uint8_t c[2];
c[0] = reg | 0x02; c[0] = reg | 0x02;
@ -136,17 +136,17 @@ void MAX3421e< SS, INTR >::regWr(uint8_t reg, uint8_t data) {
SPDR = data; SPDR = data;
while(!(SPSR & (1 << SPIF))); while(!(SPSR & (1 << SPIF)));
#endif #endif
SS::Set(); SPI_SS::Set();
XMEM_RELEASE_SPI(); XMEM_RELEASE_SPI();
return; return;
}; };
/* multiple-byte write */ /* multiple-byte write */
/* returns a pointer to memory position after last written */ /* returns a pointer to memory position after last written */
template< typename SS, typename INTR > template< typename SPI_SS, typename INTR >
uint8_t* MAX3421e< SS, INTR >::bytesWr(uint8_t reg, uint8_t nbytes, uint8_t* data_p) { uint8_t* MAX3421e< SPI_SS, INTR >::bytesWr(uint8_t reg, uint8_t nbytes, uint8_t* data_p) {
XMEM_ACQUIRE_SPI(); XMEM_ACQUIRE_SPI();
SS::Clear(); SPI_SS::Clear();
#if USING_SPI4TEENSY3 #if USING_SPI4TEENSY3
spi4teensy3::send(reg | 0x02); spi4teensy3::send(reg | 0x02);
spi4teensy3::send(data_p, nbytes); spi4teensy3::send(data_p, nbytes);
@ -160,7 +160,7 @@ uint8_t* MAX3421e< SS, INTR >::bytesWr(uint8_t reg, uint8_t nbytes, uint8_t* dat
} }
while(!(SPSR & (1 << SPIF))); while(!(SPSR & (1 << SPIF)));
#endif #endif
SS::Set(); SPI_SS::Set();
XMEM_RELEASE_SPI(); XMEM_RELEASE_SPI();
return( data_p); return( data_p);
} }
@ -168,8 +168,8 @@ uint8_t* MAX3421e< SS, INTR >::bytesWr(uint8_t reg, uint8_t nbytes, uint8_t* dat
/*GPIO byte is split between 2 registers, so two writes are needed to write one byte */ /*GPIO byte is split between 2 registers, so two writes are needed to write one byte */
/* GPOUT bits are in the low nibble. 0-3 in IOPINS1, 4-7 in IOPINS2 */ /* GPOUT bits are in the low nibble. 0-3 in IOPINS1, 4-7 in IOPINS2 */
template< typename SS, typename INTR > template< typename SPI_SS, typename INTR >
void MAX3421e< SS, INTR >::gpioWr(uint8_t data) { void MAX3421e< SPI_SS, INTR >::gpioWr(uint8_t data) {
regWr(rIOPINS1, data); regWr(rIOPINS1, data);
data >>= 4; data >>= 4;
regWr(rIOPINS2, data); regWr(rIOPINS2, data);
@ -177,20 +177,20 @@ void MAX3421e< SS, INTR >::gpioWr(uint8_t data) {
} }
/* single host register read */ /* single host register read */
template< typename SS, typename INTR > template< typename SPI_SS, typename INTR >
uint8_t MAX3421e< SS, INTR >::regRd(uint8_t reg) { uint8_t MAX3421e< SPI_SS, INTR >::regRd(uint8_t reg) {
XMEM_ACQUIRE_SPI(); XMEM_ACQUIRE_SPI();
SS::Clear(); SPI_SS::Clear();
#if USING_SPI4TEENSY3 #if USING_SPI4TEENSY3
spi4teensy3::send(reg); spi4teensy3::send(reg);
uint8_t rv = spi4teensy3::receive(); uint8_t rv = spi4teensy3::receive();
SS::Set(); SPI_SS::Set();
#else #else
SPDR = reg; SPDR = reg;
while(!(SPSR & (1 << SPIF))); while(!(SPSR & (1 << SPIF)));
SPDR = 0; //send empty byte SPDR = 0; //send empty byte
while(!(SPSR & (1 << SPIF))); while(!(SPSR & (1 << SPIF)));
SS::Set(); SPI_SS::Set();
uint8_t rv = SPDR; uint8_t rv = SPDR;
#endif #endif
XMEM_RELEASE_SPI(); XMEM_RELEASE_SPI();
@ -199,10 +199,10 @@ uint8_t MAX3421e< SS, INTR >::regRd(uint8_t reg) {
/* multiple-byte register read */ /* multiple-byte register read */
/* returns a pointer to a memory position after last read */ /* returns a pointer to a memory position after last read */
template< typename SS, typename INTR > template< typename SPI_SS, typename INTR >
uint8_t* MAX3421e< SS, INTR >::bytesRd(uint8_t reg, uint8_t nbytes, uint8_t* data_p) { uint8_t* MAX3421e< SPI_SS, INTR >::bytesRd(uint8_t reg, uint8_t nbytes, uint8_t* data_p) {
XMEM_ACQUIRE_SPI(); XMEM_ACQUIRE_SPI();
SS::Clear(); SPI_SS::Clear();
#if USING_SPI4TEENSY3 #if USING_SPI4TEENSY3
spi4teensy3::send(reg); spi4teensy3::send(reg);
spi4teensy3::receive(data_p, nbytes); spi4teensy3::receive(data_p, nbytes);
@ -227,15 +227,15 @@ uint8_t* MAX3421e< SS, INTR >::bytesRd(uint8_t reg, uint8_t nbytes, uint8_t* dat
} }
#endif #endif
#endif #endif
SS::Set(); SPI_SS::Set();
XMEM_RELEASE_SPI(); XMEM_RELEASE_SPI();
return( data_p); return( data_p);
} }
/* GPIO read. See gpioWr for explanation */ /* GPIO read. See gpioWr for explanation */
/* GPIN pins are in high nibbles of IOPINS1, IOPINS2 */ /* GPIN pins are in high nibbles of IOPINS1, IOPINS2 */
template< typename SS, typename INTR > template< typename SPI_SS, typename INTR >
uint8_t MAX3421e< SS, INTR >::gpioRd() { uint8_t MAX3421e< SPI_SS, INTR >::gpioRd() {
uint8_t gpin = 0; uint8_t gpin = 0;
gpin = regRd(rIOPINS2); //pins 4-7 gpin = regRd(rIOPINS2); //pins 4-7
gpin &= 0xf0; //clean lower nibble gpin &= 0xf0; //clean lower nibble
@ -245,8 +245,8 @@ uint8_t MAX3421e< SS, INTR >::gpioRd() {
/* reset MAX3421E. Returns number of cycles it took for PLL to stabilize after reset /* reset MAX3421E. Returns number of cycles it took for PLL to stabilize after reset
or zero if PLL haven't stabilized in 65535 cycles */ or zero if PLL haven't stabilized in 65535 cycles */
template< typename SS, typename INTR > template< typename SPI_SS, typename INTR >
uint16_t MAX3421e< SS, INTR >::reset() { uint16_t MAX3421e< SPI_SS, INTR >::reset() {
uint16_t i = 0; uint16_t i = 0;
regWr(rUSBCTL, bmCHIPRES); regWr(rUSBCTL, bmCHIPRES);
regWr(rUSBCTL, 0x00); regWr(rUSBCTL, 0x00);
@ -259,15 +259,15 @@ uint16_t MAX3421e< SS, INTR >::reset() {
} }
/* initialize MAX3421E. Set Host mode, pullups, and stuff. Returns 0 if success, -1 if not */ /* initialize MAX3421E. Set Host mode, pullups, and stuff. Returns 0 if success, -1 if not */
template< typename SS, typename INTR > template< typename SPI_SS, typename INTR >
int8_t MAX3421e< SS, INTR >::Init() { int8_t MAX3421e< SPI_SS, INTR >::Init() {
XMEM_ACQUIRE_SPI(); XMEM_ACQUIRE_SPI();
// Moved here. // Moved here.
// you really should not init hardware in the constructor when it involves locks. // you really should not init hardware in the constructor when it involves locks.
// Also avoids the vbus flicker issue confusing some devices. // Also avoids the vbus flicker issue confusing some devices.
/* pin and peripheral setup */ /* pin and peripheral setup */
SS::SetDirWrite(); SPI_SS::SetDirWrite();
SS::Set(); SPI_SS::Set();
spi::init(); spi::init();
INTR::SetDirRead(); INTR::SetDirRead();
XMEM_RELEASE_SPI(); XMEM_RELEASE_SPI();
@ -296,15 +296,15 @@ int8_t MAX3421e< SS, INTR >::Init() {
} }
/* initialize MAX3421E. Set Host mode, pullups, and stuff. Returns 0 if success, -1 if not */ /* initialize MAX3421E. Set Host mode, pullups, and stuff. Returns 0 if success, -1 if not */
template< typename SS, typename INTR > template< typename SPI_SS, typename INTR >
int8_t MAX3421e< SS, INTR >::Init(int mseconds) { int8_t MAX3421e< SPI_SS, INTR >::Init(int mseconds) {
XMEM_ACQUIRE_SPI(); XMEM_ACQUIRE_SPI();
// Moved here. // Moved here.
// you really should not init hardware in the constructor when it involves locks. // you really should not init hardware in the constructor when it involves locks.
// Also avoids the vbus flicker issue confusing some devices. // Also avoids the vbus flicker issue confusing some devices.
/* pin and peripheral setup */ /* pin and peripheral setup */
SS::SetDirWrite(); SPI_SS::SetDirWrite();
SS::Set(); SPI_SS::Set();
spi::init(); spi::init();
INTR::SetDirRead(); INTR::SetDirRead();
XMEM_RELEASE_SPI(); XMEM_RELEASE_SPI();
@ -340,8 +340,8 @@ int8_t MAX3421e< SS, INTR >::Init(int mseconds) {
} }
/* probe bus to determine device presence and speed and switch host to this speed */ /* probe bus to determine device presence and speed and switch host to this speed */
template< typename SS, typename INTR > template< typename SPI_SS, typename INTR >
void MAX3421e< SS, INTR >::busprobe() { void MAX3421e< SPI_SS, INTR >::busprobe() {
uint8_t bus_sample; uint8_t bus_sample;
bus_sample = regRd(rHRSL); //Get J,K status bus_sample = regRd(rHRSL); //Get J,K status
bus_sample &= (bmJSTATUS | bmKSTATUS); //zero the rest of the byte bus_sample &= (bmJSTATUS | bmKSTATUS); //zero the rest of the byte
@ -375,8 +375,8 @@ void MAX3421e< SS, INTR >::busprobe() {
} }
/* MAX3421 state change task and interrupt handler */ /* MAX3421 state change task and interrupt handler */
template< typename SS, typename INTR > template< typename SPI_SS, typename INTR >
uint8_t MAX3421e< SS, INTR >::Task(void) { uint8_t MAX3421e< SPI_SS, INTR >::Task(void) {
uint8_t rcode = 0; uint8_t rcode = 0;
uint8_t pinvalue; uint8_t pinvalue;
//USB_HOST_SERIAL.print("Vbus state: "); //USB_HOST_SERIAL.print("Vbus state: ");
@ -394,8 +394,8 @@ uint8_t MAX3421e< SS, INTR >::Task(void) {
return( rcode); return( rcode);
} }
template< typename SS, typename INTR > template< typename SPI_SS, typename INTR >
uint8_t MAX3421e< SS, INTR >::IntHandler() { uint8_t MAX3421e< SPI_SS, INTR >::IntHandler() {
uint8_t HIRQ; uint8_t HIRQ;
uint8_t HIRQ_sendback = 0x00; uint8_t HIRQ_sendback = 0x00;
HIRQ = regRd(rHIRQ); //determine interrupt source HIRQ = regRd(rHIRQ); //determine interrupt source
@ -410,8 +410,8 @@ uint8_t MAX3421e< SS, INTR >::IntHandler() {
regWr(rHIRQ, HIRQ_sendback); regWr(rHIRQ, HIRQ_sendback);
return( HIRQ_sendback); return( HIRQ_sendback);
} }
//template< typename SS, typename INTR > //template< typename SPI_SS, typename INTR >
//uint8_t MAX3421e< SS, INTR >::GpxHandler() //uint8_t MAX3421e< SPI_SS, INTR >::GpxHandler()
//{ //{
// uint8_t GPINIRQ = regRd( rGPINIRQ ); //read GPIN IRQ register // uint8_t GPINIRQ = regRd( rGPINIRQ ); //read GPIN IRQ register
//// if( GPINIRQ & bmGPINIRQ7 ) { //vbus overload //// if( GPINIRQ & bmGPINIRQ7 ) { //vbus overload