mirror of
https://github.com/felis/USB_Host_Shield_2.0.git
synced 2024-03-22 11:31:26 +01:00
Renamed CLK, MOSI, MISO and SS variables, as they conflicted with defines in pins_arduino.h
See: 7fcba37acf
This commit is contained in:
Kristian Lauszus
parent
0b2e444e7b
commit
f283e90402
1 changed files with 48 additions and 48 deletions
96
usbhost.h
96
usbhost.h
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@ -28,7 +28,7 @@ e-mail : support@circuitsathome.com
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#endif
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/* SPI initialization */
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template< typename CLK, typename MOSI, typename MISO, typename SPI_SS > class SPi {
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template< typename SPI_CLK, typename SPI_MOSI, typename SPI_MISO, typename SPI_SS > class SPi {
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#if USING_SPI4TEENSY3
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public:
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@ -46,9 +46,9 @@ public:
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static void init() {
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//uint8_t tmp;
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CLK::SetDirWrite();
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MOSI::SetDirWrite();
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MISO::SetDirRead();
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SPI_CLK::SetDirWrite();
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SPI_MOSI::SetDirWrite();
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SPI_MISO::SetDirRead();
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SPI_SS::SetDirWrite();
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/* mode 00 (CPOL=0, CPHA=0) master, fclk/2. Mode 11 (CPOL=11, CPHA=11) is also supported by MAX3421E */
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SPCR = 0x50;
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@ -78,7 +78,7 @@ typedef enum {
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vbus_off = GPX_VBDET
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} VBUS_t;
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template< typename SS, typename INTR > class MAX3421e /* : public spi */ {
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template< typename SPI_SS, typename INTR > class MAX3421e /* : public spi */ {
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static uint8_t vbusState;
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public:
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@ -106,12 +106,12 @@ public:
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uint8_t Task();
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};
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template< typename SS, typename INTR >
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uint8_t MAX3421e< SS, INTR >::vbusState = 0;
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template< typename SPI_SS, typename INTR >
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uint8_t MAX3421e< SPI_SS, INTR >::vbusState = 0;
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/* constructor */
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template< typename SS, typename INTR >
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MAX3421e< SS, INTR >::MAX3421e() {
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template< typename SPI_SS, typename INTR >
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MAX3421e< SPI_SS, INTR >::MAX3421e() {
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// Leaving ADK hardware setup in here, for now. This really belongs with the other parts.
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#ifdef BOARD_MEGA_ADK
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// For Mega ADK, which has a Max3421e on-board, set MAX_RESET to output mode, and then set it to HIGH
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@ -121,10 +121,10 @@ MAX3421e< SS, INTR >::MAX3421e() {
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};
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/* write single byte into MAX3421 register */
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template< typename SS, typename INTR >
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void MAX3421e< SS, INTR >::regWr(uint8_t reg, uint8_t data) {
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template< typename SPI_SS, typename INTR >
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void MAX3421e< SPI_SS, INTR >::regWr(uint8_t reg, uint8_t data) {
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XMEM_ACQUIRE_SPI();
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SS::Clear();
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SPI_SS::Clear();
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#if USING_SPI4TEENSY3
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uint8_t c[2];
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c[0] = reg | 0x02;
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@ -136,17 +136,17 @@ void MAX3421e< SS, INTR >::regWr(uint8_t reg, uint8_t data) {
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SPDR = data;
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while(!(SPSR & (1 << SPIF)));
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#endif
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SS::Set();
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SPI_SS::Set();
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XMEM_RELEASE_SPI();
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return;
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};
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/* multiple-byte write */
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/* returns a pointer to memory position after last written */
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template< typename SS, typename INTR >
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uint8_t* MAX3421e< SS, INTR >::bytesWr(uint8_t reg, uint8_t nbytes, uint8_t* data_p) {
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template< typename SPI_SS, typename INTR >
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uint8_t* MAX3421e< SPI_SS, INTR >::bytesWr(uint8_t reg, uint8_t nbytes, uint8_t* data_p) {
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XMEM_ACQUIRE_SPI();
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SS::Clear();
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SPI_SS::Clear();
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#if USING_SPI4TEENSY3
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spi4teensy3::send(reg | 0x02);
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spi4teensy3::send(data_p, nbytes);
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@ -160,7 +160,7 @@ uint8_t* MAX3421e< SS, INTR >::bytesWr(uint8_t reg, uint8_t nbytes, uint8_t* dat
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}
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while(!(SPSR & (1 << SPIF)));
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#endif
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SS::Set();
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SPI_SS::Set();
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XMEM_RELEASE_SPI();
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return( data_p);
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}
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@ -168,8 +168,8 @@ uint8_t* MAX3421e< SS, INTR >::bytesWr(uint8_t reg, uint8_t nbytes, uint8_t* dat
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/*GPIO byte is split between 2 registers, so two writes are needed to write one byte */
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/* GPOUT bits are in the low nibble. 0-3 in IOPINS1, 4-7 in IOPINS2 */
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template< typename SS, typename INTR >
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void MAX3421e< SS, INTR >::gpioWr(uint8_t data) {
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template< typename SPI_SS, typename INTR >
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void MAX3421e< SPI_SS, INTR >::gpioWr(uint8_t data) {
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regWr(rIOPINS1, data);
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data >>= 4;
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regWr(rIOPINS2, data);
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@ -177,20 +177,20 @@ void MAX3421e< SS, INTR >::gpioWr(uint8_t data) {
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}
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/* single host register read */
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template< typename SS, typename INTR >
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uint8_t MAX3421e< SS, INTR >::regRd(uint8_t reg) {
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template< typename SPI_SS, typename INTR >
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uint8_t MAX3421e< SPI_SS, INTR >::regRd(uint8_t reg) {
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XMEM_ACQUIRE_SPI();
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SS::Clear();
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SPI_SS::Clear();
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#if USING_SPI4TEENSY3
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spi4teensy3::send(reg);
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uint8_t rv = spi4teensy3::receive();
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SS::Set();
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SPI_SS::Set();
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#else
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SPDR = reg;
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while(!(SPSR & (1 << SPIF)));
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SPDR = 0; //send empty byte
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while(!(SPSR & (1 << SPIF)));
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SS::Set();
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SPI_SS::Set();
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uint8_t rv = SPDR;
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#endif
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XMEM_RELEASE_SPI();
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@ -199,10 +199,10 @@ uint8_t MAX3421e< SS, INTR >::regRd(uint8_t reg) {
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/* multiple-byte register read */
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/* returns a pointer to a memory position after last read */
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template< typename SS, typename INTR >
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uint8_t* MAX3421e< SS, INTR >::bytesRd(uint8_t reg, uint8_t nbytes, uint8_t* data_p) {
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template< typename SPI_SS, typename INTR >
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uint8_t* MAX3421e< SPI_SS, INTR >::bytesRd(uint8_t reg, uint8_t nbytes, uint8_t* data_p) {
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XMEM_ACQUIRE_SPI();
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SS::Clear();
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SPI_SS::Clear();
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#if USING_SPI4TEENSY3
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spi4teensy3::send(reg);
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spi4teensy3::receive(data_p, nbytes);
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@ -227,15 +227,15 @@ uint8_t* MAX3421e< SS, INTR >::bytesRd(uint8_t reg, uint8_t nbytes, uint8_t* dat
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}
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#endif
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#endif
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SS::Set();
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SPI_SS::Set();
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XMEM_RELEASE_SPI();
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return( data_p);
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}
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/* GPIO read. See gpioWr for explanation */
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/* GPIN pins are in high nibbles of IOPINS1, IOPINS2 */
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template< typename SS, typename INTR >
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uint8_t MAX3421e< SS, INTR >::gpioRd() {
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template< typename SPI_SS, typename INTR >
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uint8_t MAX3421e< SPI_SS, INTR >::gpioRd() {
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uint8_t gpin = 0;
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gpin = regRd(rIOPINS2); //pins 4-7
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gpin &= 0xf0; //clean lower nibble
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@ -245,8 +245,8 @@ uint8_t MAX3421e< SS, INTR >::gpioRd() {
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/* reset MAX3421E. Returns number of cycles it took for PLL to stabilize after reset
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or zero if PLL haven't stabilized in 65535 cycles */
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template< typename SS, typename INTR >
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uint16_t MAX3421e< SS, INTR >::reset() {
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template< typename SPI_SS, typename INTR >
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uint16_t MAX3421e< SPI_SS, INTR >::reset() {
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uint16_t i = 0;
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regWr(rUSBCTL, bmCHIPRES);
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regWr(rUSBCTL, 0x00);
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@ -259,15 +259,15 @@ uint16_t MAX3421e< SS, INTR >::reset() {
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}
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/* initialize MAX3421E. Set Host mode, pullups, and stuff. Returns 0 if success, -1 if not */
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template< typename SS, typename INTR >
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int8_t MAX3421e< SS, INTR >::Init() {
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template< typename SPI_SS, typename INTR >
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int8_t MAX3421e< SPI_SS, INTR >::Init() {
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XMEM_ACQUIRE_SPI();
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// Moved here.
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// you really should not init hardware in the constructor when it involves locks.
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// Also avoids the vbus flicker issue confusing some devices.
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/* pin and peripheral setup */
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SS::SetDirWrite();
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SS::Set();
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SPI_SS::SetDirWrite();
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SPI_SS::Set();
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spi::init();
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INTR::SetDirRead();
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XMEM_RELEASE_SPI();
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@ -296,15 +296,15 @@ int8_t MAX3421e< SS, INTR >::Init() {
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}
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/* initialize MAX3421E. Set Host mode, pullups, and stuff. Returns 0 if success, -1 if not */
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template< typename SS, typename INTR >
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int8_t MAX3421e< SS, INTR >::Init(int mseconds) {
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template< typename SPI_SS, typename INTR >
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int8_t MAX3421e< SPI_SS, INTR >::Init(int mseconds) {
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XMEM_ACQUIRE_SPI();
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// Moved here.
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// you really should not init hardware in the constructor when it involves locks.
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// Also avoids the vbus flicker issue confusing some devices.
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/* pin and peripheral setup */
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SS::SetDirWrite();
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SS::Set();
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SPI_SS::SetDirWrite();
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SPI_SS::Set();
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spi::init();
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INTR::SetDirRead();
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XMEM_RELEASE_SPI();
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@ -340,8 +340,8 @@ int8_t MAX3421e< SS, INTR >::Init(int mseconds) {
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}
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/* probe bus to determine device presence and speed and switch host to this speed */
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template< typename SS, typename INTR >
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void MAX3421e< SS, INTR >::busprobe() {
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template< typename SPI_SS, typename INTR >
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void MAX3421e< SPI_SS, INTR >::busprobe() {
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uint8_t bus_sample;
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bus_sample = regRd(rHRSL); //Get J,K status
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bus_sample &= (bmJSTATUS | bmKSTATUS); //zero the rest of the byte
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@ -375,8 +375,8 @@ void MAX3421e< SS, INTR >::busprobe() {
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}
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/* MAX3421 state change task and interrupt handler */
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template< typename SS, typename INTR >
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uint8_t MAX3421e< SS, INTR >::Task(void) {
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template< typename SPI_SS, typename INTR >
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uint8_t MAX3421e< SPI_SS, INTR >::Task(void) {
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uint8_t rcode = 0;
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uint8_t pinvalue;
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//USB_HOST_SERIAL.print("Vbus state: ");
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@ -394,8 +394,8 @@ uint8_t MAX3421e< SS, INTR >::Task(void) {
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return( rcode);
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}
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template< typename SS, typename INTR >
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uint8_t MAX3421e< SS, INTR >::IntHandler() {
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template< typename SPI_SS, typename INTR >
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uint8_t MAX3421e< SPI_SS, INTR >::IntHandler() {
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uint8_t HIRQ;
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uint8_t HIRQ_sendback = 0x00;
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HIRQ = regRd(rHIRQ); //determine interrupt source
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@ -410,8 +410,8 @@ uint8_t MAX3421e< SS, INTR >::IntHandler() {
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regWr(rHIRQ, HIRQ_sendback);
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return( HIRQ_sendback);
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}
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//template< typename SS, typename INTR >
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//uint8_t MAX3421e< SS, INTR >::GpxHandler()
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//template< typename SPI_SS, typename INTR >
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//uint8_t MAX3421e< SPI_SS, INTR >::GpxHandler()
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//{
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// uint8_t GPINIRQ = regRd( rGPINIRQ ); //read GPIN IRQ register
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//// if( GPINIRQ & bmGPINIRQ7 ) { //vbus overload
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