19 #if !defined(__CDC_XR21B1411_H__) 20 #define __CDC_XR21B1411_H__ 24 #define XR_REG_CUSTOM_DRIVER (0x020DU) // DRIVER SELECT 25 #define XR_REG_CUSTOM_DRIVER_ACTIVE (0x0001U) // 0: CDC 1: CUSTOM 27 #define XR_REG_ACM_FLOW_CTL (0x0216U) // FLOW CONTROL REGISTER CDCACM MODE 28 #define XR_REG_FLOW_CTL (0x0C06U) // FLOW CONTROL REGISTER CUSTOM MODE 29 #define XR_REG_FLOW_CTL_HALF_DPLX (0x0008U) // 0:FULL DUPLEX 1:HALF DUPLEX 30 #define XR_REG_FLOW_CTL_MODE_MASK (0x0007U) // MODE BITMASK 31 #define XR_REG_FLOW_CTL_NONE (0x0000U) // NO FLOW CONTROL 32 #define XR_REG_FLOW_CTL_HW (0x0001U) // HARDWARE FLOW CONTROL 33 #define XR_REG_FLOW_CTL_SW (0x0002U) // SOFTWARE FLOW CONTROL 34 #define XR_REG_FLOW_CTL_MMMRX (0x0003U) // MULTIDROP RX UPON ADDRESS MATCH 35 #define XR_REG_FLOW_CTL_MMMRXTX (0x0004U) // MULTIDROP RX/TX UPON ADDRESS MATCH 37 #define XR_REG_ACM_GPIO_MODE (0x0217U) // GPIO MODE REGISTER IN CDCACM MODE 38 #define XR_REG_GPIO_MODE (0x0C0CU) // GPIO MODE REGISTER IN CUSTOM MODE 39 #define XR_REG_GPIO_MODE_GPIO (0x0000U) // ALL GPIO PINS ACM PROGRAMMABLE 40 #define XR_REG_GPIO_MODE_FC_RTSCTS (0x0001U) // AUTO RTSCTS HW FC (GPIO 4/5) 41 #define XR_REG_GPIO_MODE_FC_DTRDSR (0x0002U) // AUTO DTRDSR HW FC (GPIO 2/3) 42 #define XR_REG_GPIO_MODE_ATE (0x0003U) // AUTO TRANSCEIVER ENABLE DURING TX (GPIO 5) 43 #define XR_REG_GPIO_MODE_ATE_ADDRESS (0x0004U) // AUTO TRANSCEIVER ENABLE ON ADDRESS MATCH (GPIO 5) 45 #define XR_REG_ACM_GPIO_DIR (0x0218U) // GPIO DIRECTION REGISTER CDCACM MODE, 0:IN 1:OUT 46 #define XR_REG_GPIO_DIR (0x0C0DU) // GPIO DIRECTION REGISTER CUSTOM MODE, 0:IN 1:OUT 48 #define XR_REG_ACM_GPIO_INT (0x0219U) // GPIO PIN CHANGE INTERRUPT ENABLE CDCACM MODE, 0: ENABLED 1: DISABLED 49 #define XR_REG_GPIO_INT (0x0C11U) // GPIO PIN CHANGE INTERRUPT ENABLE CUSTOM MODE, 0: ENABLED 1: DISABLED 50 #define XR_REG_GPIO_MASK (0x001FU) // GPIO REGISTERS BITMASK 52 #define XR_REG_UART_ENABLE (0x0C00U) // UART I/O ENABLE REGISTER 53 #define XR_REG_UART_ENABLE_RX (0x0002U) // 0:DISABLED 1:ENABLED 54 #define XR_REG_UART_ENABLE_TX (0x0001U) // 0:DISABLED 1:ENABLED 56 #define XR_REG_ERROR_STATUS (0x0C09U) // ERROR STATUS REGISTER 57 #define XR_REG_ERROR_STATUS_MASK (0x00F8U) // ERROR STATUS BITMASK 58 #define XR_REG_ERROR_STATUS_ERROR (0x0070U) // ERROR STATUS ERROR BITMASK 59 #define XR_REG_ERROR_STATUS_BREAK (0x0008U) // BREAK HAS BEEN DETECTED 60 #define XR_REG_ERROR_STATUS_OVERRUN (0x0010U) // RX OVERRUN ERROR 61 #define XR_REG_ERROR_STATUS_PARITY (0x0020U) // PARITY ERROR 62 #define XR_REG_ERROR_STATUS_FRAME (0x0040U) // FRAMING ERROR 63 #define XR_REG_ERROR_STATUS_BREAKING (0x0080U) // BREAK IS BEING DETECTED 65 #define XR_REG_TX_BREAK (0x0C0AU) // TRANSMIT BREAK. 0X0001-0XFFE TIME IN MS, 0X0000 STOP, 0X0FFF BREAK ON 67 #define XR_REG_XCVR_EN_DELAY (0x0C0BU) // TURN-ARROUND DELAY IN BIT-TIMES 0X0000-0X000F 69 #define XR_REG_GPIO_SET (0x0C0EU) // 1:SET GPIO PIN 71 #define XR_REG_GPIO_CLR (0x0C0FU) // 1:CLEAR GPIO PIN 73 #define XR_REG_GPIO_STATUS (0x0C10U) // READ GPIO PINS 75 #define XR_REG_CUSTOMISED_INT (0x0C12U) // 0:STANDARD 1:CUSTOM SEE DATA SHEET 77 #define XR_REG_PIN_PULLUP_ENABLE (0x0C14U) // 0:DISABLE 1:ENABLE, BITS 0-5:GPIO, 6:RX 7:TX 79 #define XR_REG_PIN_PULLDOWN_ENABLE (0x0C15U) // 0:DISABLE 1:ENABLE, BITS 0-5:GPIO, 6:RX 7:TX 81 #define XR_REG_LOOPBACK (0x0C16U) // 0:DISABLE 1:ENABLE, SEE DATA SHEET 83 #define XR_REG_RX_FIFO_LATENCY (0x0CC2U) // FIFO LATENCY REGISTER 84 #define XR_REG_RX_FIFO_LATENCY_ENABLE (0x0001U) // 86 #define XR_REG_WIDE_MODE (0x0D02U) 87 #define XR_REG_WIDE_MODE_ENABLE (0x0001U) 89 #define XR_REG_XON_CHAR (0x0C07U) 90 #define XR_REG_XOFF_CHAR (0x0C08U) 92 #define XR_REG_TX_FIFO_RESET (0x0C80U) // 1: RESET, SELF-CLEARING 93 #define XR_REG_TX_FIFO_COUNT (0x0C81U) // READ-ONLY 94 #define XR_REG_RX_FIFO_RESET (0x0CC0U) // 1: RESET, SELF-CLEARING 95 #define XR_REG_RX_FIFO_COUNT (0x0CC1U) // READ-ONLY 97 #define XR_WRITE_REQUEST_TYPE (0x40U) 99 #define XR_READ_REQUEST_TYPE (0xC0U) 101 #define XR_MAX_ENDPOINTS 4 115 virtual bool VIDPIDOK(uint16_t vid, uint16_t pid) {
116 return (((vid == 0x2890U) && (pid == 0x0201U)) || ((vid == 0x04e2U) && (pid == 0x1411U)));
119 uint8_t
Init(uint8_t parent, uint8_t port,
bool lowspeed);
133 return (
pUsb->
ctrlReq(
bAddress, 0,
XR_READ_REQUEST_TYPE, 1, 0, 0, reg, 2, 2, (uint8_t *)val, NULL));
137 return (
pUsb->
ctrlReq(
bAddress, 0,
XR_WRITE_REQUEST_TYPE, 0,
BGRAB0(val),
BGRAB1(val), reg, 0, 0, NULL, NULL));
272 #endif // __CDCPROLIFIC_H__ virtual void autoflowRTS(bool s)
#define XR_REG_ACM_FLOW_CTL
uint8_t write_register(uint16_t reg, uint16_t val)
uint8_t Init(uint8_t parent, uint8_t port, bool lowspeed)
#define XR_WRITE_REQUEST_TYPE
virtual void half_duplex(bool s)
uint8_t ctrlReq(uint8_t addr, uint8_t ep, uint8_t bmReqType, uint8_t bRequest, uint8_t wValLo, uint8_t wValHi, uint16_t wInd, uint16_t total, uint16_t nbytes, uint8_t *dataptr, USBReadParser *p)
XR21B1411(USB *pusb, CDCAsyncOper *pasync)
#define XR_REG_GPIO_MODE_FC_DTRDSR
uint8_t GetLineCoding(LINE_CODING *dataptr)
#define XR_REG_FLOW_CTL_HW
virtual void autoflowXON(bool s)
#define XR_REG_FLOW_CTL_SW
#define XR_READ_REQUEST_TYPE
virtual bool VIDPIDOK(uint16_t vid, uint16_t pid)
uint8_t SetLineCoding(const LINE_CODING *dataptr)
#define XR_REG_FLOW_CTL_HALF_DPLX
virtual tty_features enhanced_features(void)
virtual void autoflowDSR(bool s)
uint8_t read_register(uint16_t reg, uint16_t *val)
#define XR_REG_ACM_GPIO_MODE
tty_features _enhanced_status
#define XR_REG_GPIO_MODE_GPIO
#define XR_REG_FLOW_CTL_MODE_MASK